Lead frame and semiconductor device using the same

ABSTRACT

A lead frame has a die stage for mounting a semiconductor chip whose electrodes are electrically connected with leads via bonding wires, wherein they are enclosed in a molded resin, thus producing a semiconductor device. The outline of the die stage is shaped so as to be smaller than the outline of the semiconductor chip, and a plurality of cutouts are formed in the peripheral portion of the die stage so as to reduce the overall area of the die stage and to enhance the adhesion between the die stage and molded resin. The length L2 of each cutout ranges from (L1×0.05) to (L1×0.20) where L 1  denotes the length of each side of the die stage, and the overall area S2 of the die stage ranges from (S1×0.10) to (S1×0.40) where S1 denotes the overall area of the semiconductor chip.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to lead frames and semiconductor devices in whichsemiconductor chips mounted on lead frames are encapsulated in resins.

This application claims priority based on Japanese Patent ApplicationNo. 2003-151378 and Japanese Patent Application No. 2004-133376, thecontents of which are incorporated herein by reference.

2. Description of the Related Art

FIGS. 19 and 20 show an example of a semiconductor device (designated byreference numeral ‘20’) encapsulated in a resin, and comprises a leadframe 11 made of a prescribed metal such as Cu alloy and 42 alloy, asemiconductor chip 18 that is joined with the upper surface of a diestage 12 of the lead frame 11 via a joining material 17 such as Ag pasteand solder paste, a plurality of bonding wires 16 that electricallyconnect together electrodes of the semiconductor chip 18 and leads 15 ofthe lead frame 11, and a molded resin 19 made of a thermosetting resinsuch as epoxy resin for enclosing inner leads 15 a of the leads 15, etc.

The semiconductor device 20 having the aforementioned constitution istemporarily mounted at a prescribed position of a circuit board, whichis installed in an electronic device, and is then subjected to reflowsoldering in which solder paste is melted and then solidified so thatouter leads 15 b of the leads 15 electrically join the circuit board,whereby it is possible to reliably mount the semiconductor device 20 atthe prescribed position of the circuit board.

Conventionally, Sn-Pb solder (or Sn-Pb alloy) is used for thesemiconductor device 20 to be mounted on the circuit board, whereinsince a toxic substance such as lead (Pb) contained in the Sn-Pb soldermay cause possible destruction of the natural environment and may havebad effects on human bodies, the Sn-Pb solder is recently being replacedwith non-lead solder such as Sn-Ag-Cu alloy.

The non-lead solder may be advantageous for the protection of theenvironment because it does not contain toxic substance (or harmfulmaterial) such as lead (Pb); however, the melting point thereof (about217° C.) is higher than that of the Sb-Pn solder (about 183° C.);therefore, it is necessary to increase the heating temperature in reflowsoldering, whereby it is necessary to correspondingly increase the heatresistance in soldering with respect to the semiconductor device 20.

When the aforementioned semiconductor device 20 is heated upon reflowsoldering, there occur easy-to-separate portions and hard-to-separateportions due to the relationship between different materials used forthe constituent elements thereof. That is, relatively high adhesion isestablished in the boundary between the semiconductor chip 10 made ofsilicon and the molded resin 19, which may be therefore hard to separatefrom each other, while relatively low adhesion is established in theboundary between the die stage 12 made of the prescribed metal such as42 alloy and the molded resin 19, which may be therefore easy toseparate from each other. When separation occurs in the boundary betweenthe die stage 12 and the molded resin 19, due to impact caused by theseparation, the separated area extends towards the boundary between thesemiconductor chip 18 and the molded resin 19, whereby it may grow as acrack (or cracks) so as to unexpectedly break the bonding wires 16. Sucha phenomenon appears remarkably as the heating temperature in the reflowsoldering becomes higher; hence, it is necessary to take appropriatemeasures to avoid occurrence this phenomenon.

Japanese Patent Application Publication No. 2000-49272 (see pages 4-5and 7, as well as FIGS. 1, 2, and 19) discloses another example of asemiconductor device (designated by reference numeral ‘30’) in which asshown in FIGS. 21 to 23, a die stage 22 of a lead frame 21 is formed inan X-shape so as to reduce the overall joining area formed between thedie stage 22 and a molded resin 29.

Japanese Patent Application Publication No. H07-211852 (see pages 2 and4 as well as FIGS. 5 and 11) discloses a further example of asemiconductor device (designated by reference numeral ‘40’) in which asshown in FIGS. 24 and 25, an opening 32 a is formed at the centerportion of a die stage 32 of a lead frame 31 so as to reduce the overalljoining area between the die stage 32 and a molded resin 39.

The aforementioned semiconductor device 30 is designed to reduce theadhered area formed between the die stage 22 and the molded resin 29 sothat the separated area appearing in the boundary between them can bereduced, whereby it may be difficult for the separated area to extendtowards the boundary between the semiconductor chip and the moldedresin, regardless of the impact caused by the separation. However, whenthe semiconductor device 30 is joined to the circuit board by use ofnon-lead solder having a high melting point, separation may be easilycaused due to heating.

In the semiconductor device 40, the peripheral portion of the die stage32 extends outside of the peripheral portion of the semiconductor chip38, so that separation may occur in such an ‘extended’ peripheralportion to cause impact by which the separated area may be furtherextended towards the boundary between the semiconductor chip 38 and themolded resin 39, whereby it may grow as a crack (or cracks) so as tounexpectedly break bonding wires 36.

SUMMARY OF THE INVENTION

It is an object of the invention to provide a lead frame and asemiconductor device, wherein bonding wires are not broken due to cracksunexpectedly formed in a molded resin in a heating step when thesemiconductor device is mounted on a circuit board.

It is another object of the invention to provide a lead frame and asemiconductor device which can be manufactured at a high yield andtherefore contribute to the protection of the environment.

A lead frame of this invention has a die stage for mounting asemiconductor chip thereon and is enclosed in a molded resin such thatthe semiconductor chip is adhered to the upper surface of the die stage,thus producing a semiconductor device, wherein the outline of the diestage is shaped to be smaller than the outline of the semiconductorchip, and a plurality of cutouts are formed on the respective sides ofthe die stage so as to reduce the overall area of the die stage.

In the above, the die stage has a rectangular shape (or a square shape),and the cutouts are formed inwardly in the peripheral area correspondingto the four sides of the die stage. Herein, each of the cutouts has asemicircular shape whose length L2 is defined in a range from (L1×0.05)to (L1×0.20) where ‘L1’ denotes the length of each side of the diestage. In addition, the overall area S2 of the die stage is defined in arange from (S1×0.10) to (S1×0.40) where ‘S1’ denotes the overall area ofthe semiconductor chip.

The joined area between the die stage and the semiconductor chip thatare firmly joined together is surrounded by the molded resin introducedinto the cutouts of the die stage; therefore, it is possible toestablish a firmly joined state between the semiconductor chip and themolded resin inside of the cutouts of the die stage. Hence, even whenseparation occurs in the boundary between the die stage and the moldedresin, it does not extend towards the boundary between the semiconductorchip and the molded resin. That is, it is possible to prevent theseparation from growing as cracks causing possible breaks of bondingwires. The aforementioned relationships defined between L1 and L2 andbetween S1 and S2 guarantee a high joining strength between the diestage and the semiconductor chip so as to prevent separation fromoccurring in the boundary between the semiconductor chip and the moldedresin.

When the semiconductor device is installed in an electronic device, theaforementioned lead frame is joined with a circuit board by use ofnon-lead solder, which does not contain a toxic substance, thuscontributing to the protection of the environment during manufacturing.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, aspects, and embodiments of the presentinvention will be described in more detail with reference to thefollowing drawings, in which:

FIG. 1 is a cross sectional view showing the constitution of asemiconductor device having a lead frame in accordance with a firstembodiment of the invention;

FIG. 2 is an illustration diagrammatically showing the lead frame havinga die stage of a prescribed shape, which is observed from the backside;

FIG. 3 is an illustration diagrammatically showing applied areas of ajoining material on the die stage shown in FIG. 2;

FIG. 4 is a graph showing variations of S2/S1 ratio between the backsidearea (S2) of a die stage and the backside area (S1) of a semiconductorchip having 4 mm X 4 mm dimensions;

FIG. 5 is a graph showing variations of adhesive force establishedbetween the die stage and the semiconductor chip having 4 mm×4 mmdimensions;

FIG. 6 is a graph showing variations of the S2/S1 ratio between thebackside area (S2) of a die stage and the backside area (S1) of asemiconductor chip having 7 mm×7 mm dimensions;

FIG. 7 is a graph showing variations of the adhesive force establishedbetween the die stage and the semiconductor chip having 7 mm×7 mmdimensions;

FIG. 8 is a graph showing variations of the S2/S1 ratio between thebackside area (S2) of a die stage and the backside area (S1) of asemiconductor chip having 10 mm×10 mm dimensions;

FIG. 9 is a graph showing variations of the adhesive force establishedbetween the die stage and the semiconductor chip having 10 mm×10 mmdimensions;

FIG. 10 is a graph showing variations of the S2/S1 ratio between thebackside area (S2) of a die stage and the backside area (S1) of asemiconductor chip having 12 mm×12 mm dimensions;

FIG. 11 is a graph showing variations of the adhesive force establishedbetween the die stage and the semiconductor chip having 12 mm×12 mmdimensions;

FIG. 12A is a backside view diagrammatically showing a semiconductorchip and a die stage of a lead frame in accordance with a secondembodiment of the invention;

FIG. 12B is a cross sectional view taken along line A-A in FIG. 12A;

FIG. 13A is a backside view diagrammatically showing a semiconductorchip and a die stage of a lead frame in accordance with a thirdembodiment of the invention;

FIG. 13B is a cross sectional view take along line B-B in FIG. 13A;

FIG. 14 is a backside view diagrammatically showing a semiconductor chipand a die stage of a lead frame in accordance with a fourth embodimentof the invention;

FIG. 15A is a backside view diagrammatically showing a semiconductorchip and a die stage of a lead frame in accordance with a fifthembodiment of the invention;

FIG. 15B is a cross sectional view taken along line C-C in FIG. 15A;FIG. 16A is a backside view diagrammatically showing a semiconductorchip and a die stage of a lead frame in accordance with a sixthembodiment of the invention;

FIG. 16B is a cross sectional view taken along line D-D in FIG. 16A;

FIG. 17 is a backside view diagrammatically showing a semiconductor chipand a die stage of a lead frame in accordance with a seventh embodimentof the invention;

FIG. 18A is a backside view diagrammatically showing a semiconductorchip and a die stage of a lead frame in accordance with an eighthembodiment of the invention;

FIG. 18B is a cross sectional view taken along line E-E in FIG. 18A;

FIG. 19 is a cross sectional view showing the constitution of aconventionally-known semiconductor device;

FIG. 20 is a plan view simply showing the relationship between asemiconductor chip and a die stage in the semiconductor device shown inFIG. 19;

FIG. 21 is a plan view diagrammatically showing an example of the leadframe;

FIG. 22 is a plan view diagrammatically showing a semiconductor chipthat is mounted on the lead frame shown in FIG. 21;

FIG. 23 is a cross sectional view showing the constitution of aconventionally-known semiconductor device having the lead frame shown inFIG. 21;

FIG. 24 is a plan view diagrammatically showing an example of the leadframe;

FIG. 25 is a perspective view showing the appearance of aconventionally-known semiconductor device having the lead frame shown inFIG. 24;

FIG. 26 shows a comparison between samples with respect to theirdimensions and adhesive forces; and

FIG. 27 shows a comparison between samples with respect to theirdefects.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

This invention will be described in further detail by way of exampleswith reference to the accompanying drawings.

FIGS. 1 to 3 show a lead frame 1 and a semiconductor device 10 inaccordance with a first embodiment of the invention. The lead frame 1 isproduced using a thin plate made of a prescribed metal such as Cu alloyand 42 alloy, which is subjected to etching and is then subjected to diepressing, so that it is formed in a prescribed shape. Specifically, thelead frame 1 comprises a die stage 2 in which a semiconductor chip 8 ismounted on the upper surface, a plurality of stays 4 for supporting thedie stage 2, and a plurality of leads 5 that are arranged outside of thedie stage 2 and are electrically connected with electrodes of thesemiconductor chip 8.

The die stage 2 is formed in a prescribed shape to match the shape ofthe semiconductor chip 8. In the present embodiment, the die stage 2 asa whole is roughly formed in a rectangular shape to match therectangular shape of the semiconductor chip 8 as shown in FIGS. 2 and 3.

The overall area of the die stage 2 is reduced so as to be smaller thanthat of the semiconductor chip 8 (i.e., the backside area of thesemiconductor chip 8 mounted on the die stage 2), wherein the outlineshape of the die stage 2 is formed so as to be completely encompassedinside of the outline shape of the semiconductor chip 8. Hence, when thesemiconductor chip 8 is mounted on the die stage 2, the peripheralportion of the semiconductor chip 8 having the prescribed area extendsoutside of the peripheral portion of the die stage 2.

Semicircular cutouts 3 are respectively formed at the centers of thefour sides of the die stage 2, which is thus reduced in the overallarea. Therefore, when the semiconductor chip 8 is mounted on the uppersurface of the die stage 2, prescribed parts of the backside of thesemiconductor chip 8 matching the semicircular cutouts 3 of the diestage 2 are exposed towards the backside of the semiconductor chip 8.

In the above, each of the semicircular cutouts 3 is cut inside of thedie stage 2 by a prescribed length L2, which is set within a rangedefined by the following equation (1) (where L1 denotes the length ofeach side of the die stage 2).L2=(L1×0.05) to (L1×0.20)  (1)

Backside area S2 of the die stage 2 excluding the cutouts 3 is setwithin a range defined by the following equation (2) (where S1 denotesthe backside area of the semiconductor chip 8 mounted on the uppersurface of the die stage 2).S2=(S1×0.10) to (S1×0.40)  (2)

The stays 4 are formed integrally together with the die stage 2 and arearranged in a radial manner with respect to the four corners of the diestage 2, whereby the die stage 2 is reliably supported by the stays 4.

As shown in FIG. 1, the leads 5 are arranged with prescribed distancestherebetween outside of the die stage 2 so as to surround the die stage2, wherein each of the leads 5 is constituted by an inner lead 5 a,which is arranged inside of the semiconductor device 10, and an outerlead 5 b, which is arranged outside of the semiconductor device 10.

The inner leads 5 a of the leads 5 are electrically connected withelectrodes of the semiconductor chip 8 via bonding wires 6, and theouter leads 5 b are electrically joined with a circuit board (not shown)installed in an electronic device (not shown) via solder.

When the lead frame 1 having the aforementioned constitution is used toproduce the semiconductor device 10, a die bonding step is firstlyperformed in such a way that an appropriate amount of a joining material7 such as Ag paste and non-lead solder (e.g., Sn-Ag-Cu alloy) is appliedonto the upper surface of the die stage 2 of the lead frame 1, whereinthe semiconductor chip 8 is mounted on the upper surface of the diestage 2 and pressed by a prescribed load while the joining material 7 ismelted and then solidified, so that the semiconductor chip 8 isintegrally joined on the upper surface of the die stage 2.

In the above, the Ag paste and the like is applied to the upper surfaceof the die stage 2 at prescribed areas 7A (encompassed by dotted circlesin FIG. 3), which are located so as to avoid the cutouts 3. Therefore,the cutouts 3 of the die stage 2 do not interfere with the applicationof the joining material 7.

Next, in a wire bonding step, the electrodes of the semiconductor chip 8are electrically connected with the inner leads 5 a of the leads 5 byway of the bonding wires 6 such as metal wires.

Next, in a molding step, the lead frame 1 is placed in a cavity of ametal mold consisting of an upper mold and a lower mold, which is thenfilled with a thermosetting resin such as epoxy resin, which is injectedinto the cavity and is then hardened. Thus, it is possible to enclosethe semiconductor chip 8, die stage 2, bonding wires 6, and inner leads5 a of the leads 5 within a molded resin 9 made of the thermosettingresin.

In the above, the molded resin 9 flows into the cutouts 3 of the diestage 2 to join the backside of the semiconductor chip 8, so that themolded resin 9 is partially formed inside of the cutouts 3 of the diestage 2.

Next, in a lead surface processing step, non-lead solder plating isperformed on prescribed portions of the leads 5, which project outsideof the molded resin 9, as necessary, so that rust is prevented fromoccurring on the leads 5. This makes it easy to perform soldering workwhen the semiconductor device 10 is mounted on the circuit board.

Next, in a cutting and forming step, unnecessary parts of the leads arecut out so that the leads 5 are defined in prescribed lengths, whereinthe outer leads 5 b are subjected to bending so that they are formed inprescribed shapes.

Thus, it is possible to produce the semiconductor device 10 by way ofthe aforementioned steps. Then, the semiconductor device 10 having theaforementioned constitution is temporarily mounted on the circuit boardat the prescribed position, wherein non-lead solder is subjected tomelting and solidification upon reflow soldering, and the outer leads 5b of the leads 5 are electrically joined with the circuit board. Thus,it is possible to firmly mount the semiconductor device 10 on thecircuit board at the prescribed position.

In the semiconductor device 10 having the aforementioned lead frame 1,even when the semiconductor device 10 is heated upon reflow soldering sothat separation may occur between the die stage 2 and the molded resin9, it is possible to avoid the occurrence of separation between thesemiconductor chip 8 and the molded resin 9 as well as the occurrence ofbreaks of the bonding wires 6.

The present embodiment is characterized in that the outline of the diestage 2 is shaped to be smaller than the outline of the semiconductorchip 8 so that the overall area of the die stage 2 is reduced so as tobe smaller than that of the semiconductor chip 8, whereby when thesemiconductor chip 8 is mounted on the upper surface of the die stage 2,the peripheral portion of the semiconductor chip 8 partially extendsoutside of the peripheral portion of the die stage 2. Thus, it ispossible to minimize the separated area, which may be easily formed inthe peripheral portion of the die stage 2 when the semiconductor device10 is mounted on the circuit board upon heating. Hence, even whenseparation occurs between the die stage 2 and the molded resin 9, it canbe reliably prevented from extending towards the boundary between thesemiconductor chip 8 and the molded resin 9, whereby it is possible toreliably prevent the bonding wires 6 from being unexpectedly broken dueto the formation of cracks, which may be caused by the separation.

The semiconductor chip 8 is soldered to the die stage 2; hence, they canbe firmly joined together. That is, the adhered areas formed between thesemiconductor chip 8 and the molded resin 9 inside of the cutouts 3 ofthe die stage 2 are encompassed by the firmly joined areas between thedie stage 2 and the semiconductor chip 8; hence, it is possible toestablish a firmly adhered state between the semiconductor chip 8 andthe molded resin 9 inside of the cutouts 3 of the die stage 2. Inaddition, the molded resin 9 itself can be engaged inside of the cutouts3 of the die stage 2; hence, it is very difficult for both of the moldedresin 9 and the die stage 2 to mutually move from each other inprescribed directions matching the four sides of the die stage 2.Therefore, even though separation occurs between the die stage 2 and themolded resin 9, it does not extend towards the boundary between thesemiconductor chip 8 and the molded resin 9, and it does not grow ascracks to unexpectedly break the bonding wires 6.

In addition, the present embodiment introduces the relationship betweenthe length L1 of each side of the rectangularly-shaped die stage 2, andthe length L2, by which each cutout 3 is formed inwardly into each sideof the die stage 2, as defined in the aforementioned equation (1),whereby it is possible to increase the joining strength so as to behigher with respect to the die stage 2.

Even though non-lead solder, which does not contain a toxic substancesuch as lead (Pb), is used when the lead frame is joined together withthe circuit board as an environmental countermeasure, cracks are notproduced in the molded resin 9 upon heating when the semiconductordevice is firmly mounted on the circuit board so as to unexpectedlybreak the bonding wires 6; hence, it is possible to increase the yieldin the actual manufacturing of the electronic device.

Furthermore, the present embodiment introduces the relationship betweenthe backside area S1 of the semiconductor chip 8 and the backside areaS2 of the die stage 2 as defined in the aforementioned equation (2),whereby it is possible to increase the joining strength so as to behigher with respect to the die stage 2.

The aforementioned range defined in equation (2) can be explained usingan example of the semiconductor device, which is designed with thefollowing dimensions.

That is, there is provided an example of a semiconductor chip having asquare shape whose one side length is set to 4 mm, and an example of adie stage having a square shape in which semicircular cutouts are formedon respective sides, wherein the semiconductor chip and the die stageare joined together and are then integrally enclosed in a molded resin.Herein, the length L2 of each semicircular cutout is set to (L1×0.20).

FIG. 4 shows variations of a ratio S2/S1 [%], i.e., a ratio of thebackside area S2 of the die stage to the backside area S1 (=16 mm²) ofthe semiconductor chip, wherein each side of the die stage is varied inlength. The graph of FIG. 4 shows a comparison between theaforementioned example of the semiconductor device, in which cutouts areformed on the respective sides of the die stage, and a comparativeexample of the semiconductor device, in which no cutout is formed in thedie stage, in terms of the aforementioned parameter of S2/S1.

In addition, a so-called adhesive force (or adhesive factor) isintroduced to assess the adhesive property of the semiconductor device,wherein the adhesive force established between the semiconductor chipand the molded resin is normally set to 1.00, while the adhesive forceestablished between the die stage and the molded resin is decreased to0.50 when adhesion is weakened. Specifically, the adhesive force can bedescribed as follows:

FIG. 26 shows a comparison between “Sample A”, in which thesemiconductor chip has a square shape whose one side length is set to9.9 mm and the die stage has a square shape whose one side length is setto 9 mm, and “Sample B” in which the semiconductor chip has the samedimensions described above while the die stage has a square shape whoseone side length is set to 4.2 mm, wherein both of Samples A and B do notprovide cutouts in the die stages thereof.

These Samples A and B are subjected to full water content conditions;

-   -   specifically, in the pretreatment processing, they are initially        exposed to a temperature of 125° C. for 24 hours, then exposed        to a temperature of 85° C. under 30% humidity for 336 hours, and        further exposed to a temperature of 30° C. under 70% humidity        for 216 hours, so that water content is sufficiently filtrated        into them. Then, they are subjected to a heating process at        260° C. for 10 seconds, i.e., under conditions simulating the        actual reflow conditions, wherein they are subjected to        reflowing twice such that they are heated to 265° C. Thereafter,        ultrasonic examination equipment is used to perform an        examination as to the formation of cracks inside of the        semiconductor device, the occurrence of separation regarding the        die stage, and the occurrence of separation regarding the        backside of the semiconductor chip. Results are shown in FIG.        27, wherein separation inevitably occurs on the backside area of        the die stage and the backside of the semiconductor chip due to        acceleration testing.

FIG. 27 shows that since the adhesive force between the die stage andthe molded resin is relatively weak, the stage backside separation ratiois 100% with respect to both of Samples A and B, while the chip backsideseparation ratio is 82% with respect to Sample A in which S2/S1=83%, andthe chip backside separation ratio is 15% with respect to Sample B inwhich S2/S1=18%, wherein it can be said that the chip backsideseparation ratio is roughly in proportion to the ratio of the backsidearea S2 of the die stage to the backside area S1 of the semiconductorchip, i.e., S2/S1. That is, when both of the backside of thesemiconductor chip and the backside of the die stage are exposed at anequal ratio, in other words, when S2/S1=50%, it is assumed that thestage backside separation ratio is 100% while the chip backsideseparation ratio is 50%, wherein it can be said that, under the sameconditions for the comparison, the stage backside separation ratiobecomes double the chip backside separation ratio.

This is because the occurrence of separation may greatly depend upon theadhesive force of the molded resin; hence, when the adhesive forcebetween the semiconductor chip and the molded resin is 1.00, it isassumed that the adhesive force between the die stage and the moldedresin is 0.50. For this reason, it is presumed that the semiconductorchip joins the molded resin with an adhesive force of 1.00 in relationto the area (S1-S2), in which the backside area S2 of the die stage issubtracted from the backside area S1 of the semiconductor chip, whilethe die stage joins the molded resin with an adhesive force of 0.50 inrelation to the backside area S2 of the die stage. Therefore, theprescribed adhesive forces as shown in the rightmost column of FIG. 26can be defined with respect to Samples A and B respectively. Suchdefinitions for adhesive forces can be used for the assessment ofsemiconductor devices.

Under the conditions where the semiconductor chip 8 joins the die stage,the semiconductor chip 8 joins the molded resin 9 at an adhesive forceof 1.00 in relation to the ‘exposed’ backside area of the semiconductorchip 8, i.e., the aforementioned area (S1-S2), in which the backsidearea S2 of the die stage 2 excluding the cutouts 3 is subtracted fromthe backside area S1 of the semiconductor chip 8, while the die stage 2joins the molded resin 9 at an adhesive force of 0.50 in relation to thebackside area S2 of the die stage 2. FIG. 5 shows variations of theadhesive force regarding the molded resin 9 that is adhered with thesemiconductor chip 8 and the die stage 2, which join together, when oneside length of the die stage 2 is varied in consideration of theaforementioned description, wherein two curves are drawn with respect tothe formation of the cutouts 3 in the die stage 2.

It is preferable that in order to secure a sufficiently high joiningstrength regarding the die stage 2, the adhesive force be 0.80 or more.With reference to FIGS. 4 and 5, the range guaranteeing an adhesiveforce of 0.80 or more can be converted to the range of theaforementioned ratio S2/S1, which is about 40% or less. In order tosecure a relatively high adhesive established between the semiconductorchip 8 and the die stage 2, it is preferable that the ratio S2/S1 beapproximately 10% or more. That is, it is preferable that the ratioS2/S1 range from 10% to 40%, based on which the aforementioned equation(2) can be estimated.

In short, as long as the aforementioned equation (2) is satisfied, evenwhen the lead frame of the semiconductor device is joined with thecircuit board by use of non-lead solder not including a toxic substancesuch as lead (Pb), it is possible to avoid the occurrence of an event inwhich, due to the heating performed when the semiconductor device isjoined with the circuit board, cracks are formed in the molded resin soas to unexpectedly break the bonding wires; thus, it is possible toincrease the yield in manufacturing electronic devices.

To satisfy the aforementioned equation (2) in which the ratio S2/S1 isapproximately 18%, for example, a semiconductor chip having a squareshape whose one side length is set to 4 mm is joined together with a diestage having a square shape whose one side length is set to 2 mm inwhich cutouts are formed on respective sides, wherein they areintegrally enclosed in a molded resin so as to produce a semiconductordevice, which is now placed under assessment as follows:

In the assessment, the semiconductor device is subjected to baking at atemperature of 125° C. for 24 hours, humidification of 30% at 85° C. for168 hours, humifification of 70% at 30° C. for 120 hours, and heatingduring reflow soldering at a peak temperature of 265° C. for 10 seconds2 times. In this case, no separation is found with respect to the diestage; thus, very good results can be obtained.

FIGS. 6, 8, and 10 show variations of the aforementioned ratio S2/S1 inrelation to variations of one side length of the die stage with respectto three types of square-shaped semiconductor chips having 7 mmX 7 mmdimensions, 10 mm X 10 mm dimensions, and 12 mm××12 mm dimensions,respectively. In addition, FIGS. 7, 9, and 11 show variations of theadhesive force with respect to the three types of the square-shapedsemiconductor chips, respectively. Through these graphs, the range ofthe adhesive force of 0.80 or more can be translated into the range ofthe ratio S2/S1 of about 40% or less, wherein since it is preferablethat the ratio S2/S1 be approximately 10% or more, it can be generallysaid that the semiconductor device should satisfy the aforementionedequation (2).

Next, a second embodiment of the invention will be described, whereinparts identical to those used in the first embodiment are designated bythe same reference numerals; hence, the detailed description thereofwill be omitted.

FIGS. 12A and 12B show the lead frame 1 and the semiconductor device 10in accordance with the second embodiment of the invention, wherein inaddition to the foregoing cutouts 3 that are formed at the centers ofthe respective sides of the die stage 2, secondary cutouts 3A are formedso as to encompass the cutouts 3 inwardly of the die stage 2 whosebackside is subjected to half etching.

Each of the secondary cutouts 3A is opened with respect to the cutouts 3and the backside of the die stage 2, wherein in the foregoing moldingstep, the molded resin 9 flows into the secondary cutouts 3A in additionto the cutouts 3 of the die stage 2.

The second embodiment can offer the same effects as demonstrated by thefirst embodiment. In addition, due to the formation of the secondarycutouts 3A, the overall adhered area is reduced in the same plane formedbetween the backside of the die stage 2 and the molded resin 9 so thatthe stress therein is dispersed; hence, it is possible to make itdifficult for separation to occur between the die stage 2 and the moldedresin 9. Such an effect can be obtained by making the backside of thedie stage 2 roughly by use of a sand blaster and the like.

Next, a third embodiment of the invention will be described, whereinparts identical to those used in the first and second embodiments aredesignated by the same reference numerals; hence, the detaileddescription thereof will be omitted.

FIGS. 13A and 13B show the lead frame 1 and the semiconductor device 10in accordance with the third embodiment of the invention, wherein thesecondary cutouts 3A are formed by performing half etching on the uppersurface of the die stage 2 so as to encompass the semicircular cutouts3, which are formed at the centers of the respective sides of the diestage 2.

The secondary cutouts 3A are opened in the cutouts 3 on the uppersurface of the die stage 2, wherein in the foregoing molding step, themolded resin 9 is introduced into the secondary cutouts 3A in additionto the cutouts 3, so that the molded resin 9 partially formed inside ofthe secondary cutouts 3 is joined to the backside of the semiconductorchip 8.

The third embodiment can demonstrate the same effects as offered in thefirst embodiment, wherein due to the formation of the secondary cutouts3A, it is possible to increase the overall contact area between thesemiconductor chip 8 and the molded resin 9. In addition, the secondarycutouts 3A are formed in the side of the upper surface of the die stage2; hence, in the foregoing wire bonding step, it is possible to maintainthe stable condition secured for the die stage 2, which serves as thebase for mounting the semiconductor chip 8.

Next, a fourth embodiment of the invention will be described, whereinparts identical to those used in the first to third embodiments aredesignated by the same reference numerals; hence, the detaileddescription thereof will be omitted.

FIG. 14 shows the lead frame 1 and the semiconductor device 10 inaccordance with the fourth embodiment of the invention, wherein the diestage 2 is provided with through holes 3B, which penetrate through thecorner portions of the die stage 2, in addition to the semicircularcutouts 3.

Each of the through holes 3B is opened on both of the upper surface andbackside of the die stage 2, wherein in the foregoing molding step, themolded resin 9 is introduced into the insides of the through holes 3B inaddition to the cutouts 3, so that the molded resin 9 partially formedinside of the through holes 3B is joined with the backside of thesemiconductor chip 8.

The fourth embodiment can demonstrate the same effects as offered in thefirst embodiment, wherein it is possible to further increase the overallcontact area formed between the semiconductor chip 8 and the moldedresin 9. In addition, the through holes 3B do not interfere with therespective sides of the die stage 2, which form the peripheral portionof the die stage 2; hence, in the foregoing wire bonding step, it ispossible to maintain the stable condition secured for the die stage 2,which serves as the base for mounting the semiconductor chip 8.Incidentally, the fourth embodiment can be modified in such a way thatthe upper surface or backside of the die stage 2 is subjected to halfetching at prescribed areas encompassing the through holes 3B.

Next, a fifth embodiment of the invention will be described, whereinparts identical to those used in the first to fourth embodiments aredesignated by the same reference numerals; hence, the detaileddescription thereof will be omitted.

FIGS. 15A and 15B show the lead frame 1 and the semiconductor device 10in accordance with the fifth embodiment of the invention, wherein thirdcutouts 3C are formed by performing half etching on the backside of thedie stage so as to provide communication between the ‘opposing’ cutouts3, which are formed at the centers of the respective sides of the diestage 2.

The third cutouts 3C are opened between the cutouts 3 in the backside ofthe die stage 2, wherein in the foregoing molding step, the molded resin9 is introduced into the third cutouts 3C in addition to the cutouts 3.

The fifth embodiment can demonstrate the same effects as offered in thefirst embodiment, and it can also demonstrate the same effects asoffered in the second embodiment.

Next, a sixth embodiment of the invention will be described, whereinparts identical to those used in the first to fifth embodiments aredesignated by the same reference numerals; hence, the detaileddescription thereof will be omitted.

FIGS. 16A and 16B show the lead frame 1 and the semiconductor device 10in accordance with the sixth embodiment of the invention, wherein thethird cutouts 3C are formed by performing half etching on the uppersurface of the die stage 2 so as to provide communication between the‘opposing’ cutouts 3, which are formed at the centers of the respectivesides of the die stage 2.

The third cutouts 3C are opened between the cutouts 3 in the uppersurface of the die stage 2, wherein in the foregoing molding step, themolded resin 9 is introduced into the third cutouts 3C in addition tothe cutouts 3, so that the molded resin 9 partially formed in the thirdcutouts 3C is joined with the backside of the semiconductor chip 8.

The sixth embodiment can demonstrate the same effects as offered in thefirst embodiment, and it can also demonstrate the same effects asoffered in the third embodiment.

Next, a seventh embodiment of the invention will be described, whereinparts identical to those used in the first to sixth embodiments aredesignated by the same reference numerals; hence, the detaileddescription thereof will be omitted.

FIG. 17 shows the lead frame 1 and the semiconductor device 10 inaccordance with the seventh embodiment of the invention, wherein aplurality of semicircular cutouts 3 are formed on each of the four sidesof the die stage 2, so that it is possible to demonstrate the sameeffects as offered in the first embodiment.

Next, an eighth embodiment of the invention will be described, whereinparts identical to those used in the first to seventh embodiments aredesignated by the same reference numerals; hence, the detaileddescription thereof will be omitted.

FIGS. 18A and 18B show the lead frame 1 and the semiconductor device 10in accordance with the eighth embodiment of the invention, wherein aplurality of semicircular cutouts 3 are formed on each of the four sidesof the die stage 2, and fourth cutouts 3D are formed by performing halfetching on the upper surface of the peripheral portion of the die stage2 including the cutouts 3.

The fourth cutouts 3D are opened between the cutouts 3 in the uppersurface of the die stage 2 at its corners, wherein in the foregoingmolding step, the molded resin 9 is introduced into the fourth cutouts3D in addition to the cutouts 3, so that the molded resin 9 partiallyformed in the fourth cutouts 3D is joined with the backside of thesemiconductor chip 8.

The eighth embodiment can demonstrate the same effects as offered in thefirst embodiment, and it can also demonstrate the same effects asoffered in the third embodiment.

Incidentally, the cutouts 3 of the die stage 2 are not necessarilylimited to a semicircular shape, and can be changed to a triangularshape or rectangular shape, for example.

As described heretofore, this invention has a variety of effects andtechnical features, which will be described below.

(1) A semiconductor device including a lead frame according to thisinvention is designed such that the outline of a die stage is shaped tobe smaller than the outline of a semiconductor chip, whereby it ispossible to minimize the separated area that may be formed in theboundary between the die stage and molded resin due to heating when thesemiconductor device is soldered to the circuit board. This can preventthe separated area formed in proximity to the die stage from extendingto the boundary between the semiconductor chip and molded resin; hence,it is possible to prevent bonding wires from being unexpectedly brokendue to the formation of cracks caused by the growth of the separation.

(2) A plurality of cutouts are adequately formed in the peripheralportion of the die stage so that the molded resin formed inside of thecutouts can be firmly joined with the backside of the semiconductorchip. Therefore, even when separation occurs in the boundary between thedie stage and molded resin, it does not extend towards the boundarybetween the semiconductor chip and molded resin; hence, it is possibleto prevent the bonding wires from being unexpectedly broken due to theformation of cracks caused by the growth of the separation.

(3) As a result, even though non-lead solder not containing a toxicsubstance such as lead (Pb) is used to firmly combine the semiconductordevice with the circuit board, it is possible to prevent the bondingwires from being unexpectedly broken due to the formation of cracks inthe molded resin in the heating process. Thus, it is possible toincrease the yield in the manufacture of electronic devices, which maycontribute to the protection of the environment.

As this invention may be embodied in several forms without departingfrom the spirit or essential characteristics thereof, the presentembodiments are therefore illustrative and not restrictive, since thescope of the invention is defined by the appended claims rather than bythe description preceding them, and all changes that fall within metesand bounds of the claims, or equivalents of such metes and bounds aretherefore intended to be embraced by the claims.

1. A lead frame comprising: a die stage for mounting a semiconductorchip thereon, wherein an outline of the die stage is shaped to besmaller than an outline of the semiconductor chip; and a plurality ofcutouts formed in a peripheral portion of the die stage, wherein the diestage and the semiconductor chip are integrally enclosed in a moldedresin, which is introduced into the cutouts of the die stage.
 2. Thelead frame according to claim 1, wherein the die stage has a rectangularshape, so that the plurality of cutouts are formed inwardly with respectto four sides of the die stage.
 3. The lead frame according to claim 1,wherein the cutouts are accompanied by half-etched portions formedinside of the die stage.
 4. The lead frame according to claim 1, whereina plurality of secondary cutouts are formed inside of the die stage inrelation to the cutouts.
 5. The lead frame according to claim 1, whereina length L2 set for each of the cutouts is defined in a range from(L1×0.05) to (L1×0.20) where L1 denotes a length set for each side ofthe die stage.
 6. The lead frame according to claim 1, wherein anoverall area S2 of the die stage is defined in a range from (S1×0.10) to(S1×0.40) where S1 denotes an overall area of the semiconductor chip. 7.A semiconductor device comprising: a semiconductor chip; a lead framehaving a die stage for mounting the semiconductor chip thereon, whereinan outline of the die stage is shaped so as to be smaller than anoutline of the semiconductor chip; a plurality of cutouts formed in aperipheral portion of the die stage; and a molded resin for integrallyenclosing the die stage and the semiconductor chip, wherein the moldedresin is introduced into the cutouts of the die stage.
 8. Thesemiconductor device according to claim 7, wherein the die stage has arectangular shape, so that the plurality of cutouts are formed inwardlywith respect to four sides of the die stage.
 9. The semiconductor deviceaccording to claim 7, wherein the cutouts are accompanied by half-etchedportions formed inside of the die stage.
 10. The semiconductor deviceaccording to claim 7, wherein a plurality of secondary cutouts areformed inside of the die stage in relation to the cutouts.
 11. Thesemiconductor device according to claim 7, wherein a length L2 set foreach of the cutouts is defined in a range from (L1×0.05) to (L1×0.20)where L1 denotes a length set for each side of the die stage.
 12. Thesemiconductor device according to claim 7, wherein an overall area S2 ofthe die stage is defined in a range from (S1×0.10) to (S1×0.40) where S1denotes an overall area of the semiconductor chip.
 13. The semiconductordevice according to claim 7, wherein the lead frame is joined with acircuit board by use of non-lead solder.